1. Field of the Invention
The present invention relates to electronic circuits, and more particularly to logic circuits that generate logic pulses in response to coincident edges of processor clocks and bus clocks.
2. Description of Related Art
In computer systems, the processor clock usually has a far higher frequency than the bus clock. For example, in personal computers (PC's or Pentium.TM.-compatible systems), the processor clock normally runs at least twice as fast as the bus clock. As newer generations of processors become available for personal computers, processor clock speeds tend to exceed bus clock speeds by increasingly wide margins. In order to facilitate compatibility between the processor and the bus, processors are often designed so that the processor clock to bus clock ratio is a whole integer or a half integer. Typical processor clock to bus clock ratios for personal computers are listed below in Table 1.
TABLE 1 ______________________________________ PROCESSOR CLOCK TO BUS CLOCK RATIOS Processor Clock Bus Clock Frequency Frequency Ratio ______________________________________ 133 MHz 66 MHz 2 200 MHz 66 MHz 3 233 MHz 66 MHz 3.5 266 MHz 66 MHz 4 300 MHz 66 MHz 4.5 ______________________________________
Processors often include synchronization circuitry such as a phase-locked loop for establishing a timing relationship between the processor clock and the bus clock. Consequently, when the processor clock to bus clock ratio is whole integer, each rising edge of the bus clock is coincident with a rising edge of the processor clock. However, when the processor clock to bus clock ratio is a half integer, then alternating rising edges (such as even rising edges) of the bus clock are coincident with rising edges of the processor clock, and the other rising edges (such as odd rising edges) of the bus clock are not coincident with rising edges of the processor clock.
In order to coordinate operations between the processor and the bus, it may be necessary to generate a logic signal that goes active for a single processor clock cycle every time a rising edge of the processor clock coincides with a rising edge of the bus clock. In the event the processor clock to bus clock ratio is a whole integer, the logic signal becomes active upon each rising edge of the bus clock. On the other hand, when the processor clock to bus clock ratio is a half integer, the logic signal goes active only upon alternate rising edges of the bus clock.
In a processor family with similar functionality across a wide range of processor clock speeds (such as 200 MHz, 233 MHz and 266 MHz), it is highly desirable to use the same circuitry in as much of the processor as possible, despite the differing clock speeds. A logic circuit that generates the logic signal described above whenever a rising edge of the bus clock is detected is suitable when the processor clock to bus clock ratio is a whole integer but not a half integer. Similarly, a logic circuit that generates the logic signal described above whenever an alternate rising edge of the bus clock is detected is suitable when the processor clock to bus clock ratio is a half integer but not a whole integer.
Accordingly, a need exists for an even bus clock circuit that generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a range of processor clock to bus clock ratios that includes whole integers and half integers, particularly where the even bus clock circuit is compact and efficient.